The present invention relates to a semiconductor memory which is constructed of a monolithic ssemiconductor integrated circuit and, more particularly, to a Read Only Memory (ROM).
In recent years, the demand for a semiconductor memory having a large memory capacity has increased due to the progress in semiconductor technology and the development in application techniques for semiconductor devices. Unfortunately, a number of problems arise in attempting to manufacture such ROM's having a large memory capacity.
For example, the number of memory cells coupled to data lines is increased with the increase in the memory capacity. Moreover, the undesired stray or parasitic capacitance, which is liable to be coupled to the data lines, is increased with the increase in the number of the memory cells. As a result, in a data read out operation, the changing rate of the data signals, which are fed to the data lines by a selected memory cell, is restricted by the relatively large capacitance of the data lines. In other words, the driving ability of the data lines by the selected memory cell is relatively deteriorated.
The signal lines such as the data lines are frequently elongated when it is intended to increase the memory capacity. In this case, since the signal lines themselves have resistances which cannot be neglected, and since undesired capacitances having relatively large values are coupled to the signal lines, these lines experience relatively long signal delays.
In case it is intended to fabricate a semiconductor integrated circuit device having a large capacity, consideration is taken to scale down the circuit elements or wiring layers constructing the semiconductor integrated circuit device with a view to achieving a variety of objects. For example, this can prevent a reduction in the fabrication yield from being caused by the crystal defect of a semiconductor substrate. It can also prevent the area of this semiconductor substrate from being remarkably increased, and the power consumption from being highly increased. On the other hand, the signal lines thus scaled down have relatively high resistances by themselves, and thus experience long signal delays.
In order to make the responding rate of a high-capacity ROM equal to or higher than that of a low-capacity ROM, it is necessary to eliminate the adverse effects which are caused by the relative reduction in the driving ability of the data lines by the memory cell and by the increase in the delay time periods of the signal lines. Also, it is desirable from various standpoints that the power consumption of a ROM be relatively low.
On the other hand, the defects of the memory cells raise special problems in the high-capacity ROM. In this regard, in the prior art, a well-known information theory is an error correcting code which will be hereinafter referred to as "ECC". One aspect of the present invention is that a circuit for correcting errors by the use of the aforementioned ECC (which circuit will be abbreviated hereinafter as the "ECC circuit") is built in a semiconductor memory.